1. Field of the Invention
The present invention relates to a synchronization establishing and tracking circuit. More particularly, the present invention relates to a synchronization establishing and tracking circuit installed in a base station of a CDMA radio telecommunication system.
2. Description of the Related Art
Each base station in a CDMA (code division multiple access) telecommunication system forms a cell representing a control space. The cell is divided into multiple sectors for optimum use of a given wave resource. The base station thus includes communication circuits, each of which corresponds to each of the sectors. Also, provided in the base station are synchronization establishing and tracking circuits for estimating the phase of spreading codes to despread the received signal. The synchronization establishing and tracking circuits in the base station are needed the same number as of the sectors. Such techniques about the synchronization establishing tracking circuits are disclosed in Japanese Laid Open Patent Application (Jp-A-Heisei 10-28076, Jp-A-Heisei 11-17648, and Jp-A-Heisei 11-122104). Also, a matched filter circuit used in a demodulator for CDMA communication system is disclosed in Japanese Laid Open Patent Application (Jp-A-Heisei 11-274980).
FIG. 1 illustrates a conventional synchronization establishing and tracking circuit. In FIG. 1, the synchronization establishing and tracking circuit 100 is linked with three sectors. The number of the sectors is not limited to three. In a current system, six sectors are commonly used at the base station.
The synchronization establishing and tracking circuit 100 comprises first, second and third synchronization establishing and tracking portion 101a, 101b, and 101c. The first synchronization establishing and tracking portion 101a carries out a control action over the first sector. The second synchronization establishing and tracking portion 101b carries out a control action over the second sector. The third synchronization establishing and tracking portion 101c carries out a control action over the third sector.
The first synchronization establishing and tracking portion 101a includes a first correlator 102a, a first spreading code generator 103a, a first level detector 104a, a first despreading circuit 105a, a first synchronization judging circuit 106a, and a first phase shifting circuit 111a. 
The second synchronization establishing and tracking portion 101b includes a second correlator 102b, a second spreading code generator 103b, a second level detector 104b, a second despreading circuit 105b, a second synchronization judging circuit 106b, and a second phase shifting circuit 111b. 
The third synchronization establishing and tracking portion 101c includes a third correlator 102c, a third spreading code generator 103c, a third level detector 104c, a third despreading circuit 105c, a third synchronization judging circuit 106c, and a third phase shifting circuit 111c. 
The first synchronization establishing and tracking portion 101a receives a first quasi-coherent signal SS1. The second synchronization establishing and tracking portion 101b receives a second quasi-coherent signal SS2. The third synchronization establishing and tracking portion 101c receives a third quasi-coherent signal SS3.
The output of the first correlator 102a in the first synchronization establishing and tracking portion 101a is connected to the input of the first level detector 104a. The output of the first level detector 104a is connected to the input of the first despreading circuit 105a. The output of the first despreading circuit 105a is connected to the input of the first synchronization judging circuit 106a. The output of the first phase shifting circuit 111a is connected to the input of the first spreading code generator 103a. The output of the first spreading code generator 103a is connected to the first correlator 102a. The output of the first synchronization judging circuit 106a is connected to the input of the first spreading code generator 103a. 
The phase shifting circuit 111a determines the phase used in the first spreading code generator 103a. The first spreading code generator 103a generates a spreading code sequence. The phase of the spreading code sequence is sequentially shifted at a resolution lower than one chip of the spreading code. The first spreading code generator 103a is timed with the phase determined by the first phase shifting circuit 111a. The first correlator 102a takes correlation between the first quasi-coherent signal and the spreading code to produce a correlation value. The level detector 104a generates a chip synchronous signal indicative of the received phase position having the maximum correlation value. The chip synchronous signal is then used for synchronization acquisition.
Through examining the chip synchronous signal, the first despreading circuit 105a despreads the quasi-coherent signal SS1 to produce a despread signal. The first synchronization judging circuit 106a judges the synchronization based on the despread signal from the first despreading circuit 105a. When detecting the synchronization, the first synchronization judging circuit 106a informs the first spreading code generator 103a of the synchronization. This allows the first spreading code generator 103a to generate the spreading code of the phase at the timing of the synchronization.
The second and third synchronization establishing and tracking portions 101b and 101c are identical in the arrangement to the first synchronization establishing and tracking portion 101a. Also, the second and third synchronization establishing and tracking portions 101b and 101c carry out the same processing action as of the first synchronization establishing and tracking portion 101a when receiving their corresponding quasi-coherent signals SS2 and SS3.
In such a synchronization establishing and tracking circuit, the level of a received signal is detected throughout its generous bit length to decrease the effect of fading at the station. The amount of the data calculated in the correlators 102a, 102b and 102c is increased proportional to the bit length. When the calculation of the correlation is executed using a corresponding number of the correlators, its duration may be shortened. However, the higher the number of the correlators, the greater the synchronization establishing and tracking circuit will become in the circuitry arrangement, thus inhibiting the down sizing and the energy saving of the synchronization establishing and tracking circuit.